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General Info: Chip directory. Logic Families. TTL description. Comparison: TTL to HCT.

INA102 is a Burr Brown part. Features - choice of gain x10, x100, x1000 (and in-between with potentiometer). The purpose is the amplify the signal before significant noise is added to it as it travels down the wire. First stage amplifiers are always positioned near the transducer than changes the physiologic signal into an electrical signal. If it went without amplification through the circuitry, 60Hz and other noise would be imparted to the signal. Typically, physiologic signals when converted to electrical ones might have a range of millivolts or tens of millivolts. However, 60Hz noise imparted along the circuit is typically in the tens of millivolts range (you can test this by taking a bare wire and connecting it to the center lead of the BNC connector input to an oscilloscope). Let the other end be in open air. If you are inside a building the wire will pick up a tens of millivolts signal from the wall current. The signal will be a greater amplitude if the wire is lengthened. The first stage amplifier is positioned near the transducer so that relatively little additive noise is picked up and added to the signal. If the physiologic signal is 10mv p-p (peak to peak) and is amplified 100x, it then becomes a 1V p-p signal. If 10mv of noise is added to the physiologic signal after amplification, the noise level is only 1%. But if there is no amplification, the noise imparted is 100% of the signal size (10mv physiologic signal, 10mv noise). Application bulletin. Unity gain amplifier INA105.

At some point in the circuitry it may be useful to diminish rather than increase the amplitude of the signal. For this purpose a voltage (or current) divider can be used. Dividers can be constructed using resistors and use the principle of Ohm's Law. If for example we have two resistors in series, there will be a potential difference across each resistor when a current flows through them, i.e., the voltage divides itself between the two resistances. (For example, the voltage divides equally if the two resistors are equal in value). When two resistors are in parallel, current flowing across them divides itself between the two resistors according to the resistance values. (For example, the current divides equally if the two resistors are equal in value). For some diagrams of voltage and current dividers see Link 1, and to note how a divider is used in a Wheatstone Bridge see Link 2 (used in a thermistor setup; near bottom of page).

High Pass Filter (passive, 1 pole)

Capacitor (0.47m f) and resistor (200kW ). Time constant is about 100ms. "Passive" means it filters the signal without added energy, and 1 pole means that the there is a relatively weak attenuation of low frequency components. As low frequency components pass through the filter, there amplitude does not go to zero but rather, is diminished by a small amount. The higher the number of poles in the filter, the stronger the attenuation of frequencies below the cutoff (corner) frequency of the filter, which is RC/2p . Why high pass filter the signal? Only if the average level is unimportant to the physiologic measurement and/or for viewing the signal. For example, the electrocardiogram signal always has 0V mean (because it is a difference signal take from two electrodes on the body surface). A high pass filter always removes the average (DC) level and sets it to 0V. Since the electrocardiogram is a 0V signal anyway, why then might one need to use a high pass filter? Because signals are subject to drift by the electronics of the circuitry, which is imperfect, but also because of low frequency noise such as motion artifact. These DC and low frequency components are not physiologic. By using a high pass filter, they are removed, but no physiologic information is removed when the signal itself has no DC or low frequency components. Example.

Low Pass Filter (active, 5 pole)

This is an integrated circuit - LTC1062 from Linear Technology. It has selectable corner frequency 1200Hz, 600Hz, 300Hz. The corner frequency partly depends on the voltage level of an input pin (pin 4: +8V, 0V, -8V respectively). The low pass filter is used as an "anti-aliasing" filter. The Nyquist Theorem states that to prevent aliasing, the sampling rate must be at least twice that of the highest frequency component of the signal. Say the highest physiologic frequency of the signal is 500Hz. There may be higher frequencies of additive noise (say, up to several kilohertz). Using a Low Pass Filter with corner frequency of 500Hz, only physiologic components of the signal will pass through the filter. The filtered signal may then be safely sampled at a rate of 1000 Hz. It is desirable to sample at the lowest rate possible, so that the system is not tied up by unneeded samples. Anti-alias filter types. Example.

Gate (for Low pass filter)

The gate signal selects one of two capacitor values for LPF chip, which partially determines the corner frequency of the LPF. A gate allows a signal to pass through, or not. In this case the gate is for digital signals. This gate connects the capacitors in one of two ways to be connected with the low pass filter. When the gate is closed, the output is set to the high impedance level (called z). It is as though there is no connection from the output to the rest of the circuitry. When the gate is opened, whatever is at the input passes to the output and then through the rest of the circuitry. How is it useful? The gate opens or closes depending on the level of a digital signal sent to one of its input pins (high or low level). This digital signal can arise from the computer that is controlling the circuitry, which originates in the software program used to run the electronics. Therefore, the gate can be programmed to open and close in software. This is handier than to physically flip a switch on the electronics board to open or close the gate. Moreover it is much faster to use an electronic gate: maybe in takes microseconds, whereas physically reaching over and flipping a switch will take seconds (a million times slower). TTL versus HCT. Chip directory - switches.

Prevents input above ± 8V.

How could a greater input occur? If animal is defibrillated, generates a large voltage which can destroy the electrical components. At this point, only the INA102 would be rendered inoperative by a large voltage surge. The diodes work by shunting current to ground when the input voltage exceeds ± 8 volts in magnitude. It is important because too high a voltage on the input to the low pass filter chip will render it inoperable. Normally, the input voltage on any chip should not exceed the supply voltage to the chip. The actual recommended voltage is given in the specification sheet which comes with each part. Diodes are relatively inexpensive components, so in circuitry where there is a danger of vastly exceeding the supply voltage, it is very useful to included shunting diodes in the circuitry. In the configuration shown, the lower diode shunts voltages lower than -8V and the upper diode shunts voltages greater than 8V. Further description - dual diode limiter.

PGA100

This particular amplifier serves two functions: amplification and multiplexing. Three pins are devoted for amplification and three for multiplexing. The three input pins represent three bits of a binary number. A three bit binary number can represent 8 possible values. The amplification, or gain factor of this particular chip occurs in binary steps from 1 to 128, i.e., 1, 2, 4, 8, 16, 32, 64, 128. These binary-stepped gains are switched in, represented, by binary inputs of 000, 001, 010, 011, 100, 101, 110, 111. Why are binary steps used? To give the user a wider possible choice of gains. Let us consider the process further. Mechanical Specs.

Autogaining - process of adjusting the signal automatically for best input to the analog to digital converter. The process works as follows. A representative portion of the signal is acquired with a second stage amplifier set to a gain of 1. What is "representative"? A segment of the signal that is sure to include a peak maximum and peak minimum value. If the signal is periodic, there will be one peak maximum and one peak minimum value per period. For example, a signal acquired form the heart (electrical or pressure or acoustic or some other type) will approximately repeat itself once every heartbeat. In normal persons there is 1 heartbeat approximately every second. Therefore 2-3 seconds of data would be sufficient to ensure capture of a maximum and minimum peak. Once this data is acquired, it is sent through an algorithm to find the absolute maximum value that occurs during the interval. Say the original signal had an absolute maximum value of 6mv at the transduction stage. Let the first stage amplifier have a gain of 100x. this would boost the signal to 0.6V absolute maximum value. With a second stage gain of 1, the absolute maximum value detected by the software (autogaining algorithm) would also be 0.6V. Now, there is a fixed range of inputs allowed to the analog to digital converter chip that transforms the analog signal to a digital one (see more about that below). Let the allowable range into the analog to digital converter be ± 10V (typical). The gain on our signal that would boost its amplitude to just match the allowable range would be 10V/0.6V = 16.7. However, the actual gains that can be programmed into the chip are binary steps. To ensure that the autogained signal is not boosted past the allowable range, we choose the closest binary step gain below 16.7, which is 16. At this stage, the program would send a binary 110 to the three input pins on the chip, in other words, commanding it to set the gain to 16. That would adjust the signal for a maximum amplitude of 16 x 0.6V = 9.6V, which remains within the ± 10V range. Of course, a subsequent peak may exceed 6mv - the sampled interview is not always entirely representative of all possible data. This would cause "clipping" - meaning that the signal is cropped, or flattened, along any peaks that exceed the ± 10V limit. It may be useful, therefore, to gain the signal using one binary step lower, i.e., 8x, to prevent clipping.

The other component of this chip is the multiplexer. This is an 8 in, 1 out multiplexer. In effect it acts as a gate, like the one we described above, except that it is configured to gate 1 of 8 inputs to the output. To select 1 of 8, as one might have surmised, can be done using three input pins to form a 3 bit binary command to the chip called "channel select". To select channel 1, 2, 3, ... 8, the input to these three pins would be 000, 001, 010, ..., 111. These commands can also be issued by a software algorithm. What type of software algorithm? Well, typically signal channels are digitized sequentially. So, we would probably issue successive commands of 000, 001, 010, ..., to the channel select pins to sequentially digitize signals from input channels 1, 2, 3, ...., 8.

DG211

Our data acquisition board is actually designed to acquire data from 16 channels. Since the second stage amplifier can only select from a maximum of 8 inputs, and what we really need is a select 1 of 16, two PGA100 IC's are used in conjunction with the DG211 gate. Each PGA100 selects 1 of 8 inputs to be sent to the chip outputs. Then the DG211 gate selects 1 of the 2 PGA100 outputs (i.e. it is a 2 to 1 multiplexer). This combination effectively selects 1 of 16. This gate is also controlled from software. More about the control algorithm later.

SHC5320

This integrated circuit receives the signal selected by the DG211 gate, which is still an analog signal. During sample (track) mode, the output pin on this chip follows the input pin (the signal at the input and at the output is identical). There is an input pin on this chip that commands it to track or hold (low or high voltage level). When it is commanded to hold, whatever level the signal is at the input at that moment, which also appears at the output, will remain at the output. The output will be held at the level until the track/hold pin is again commanded to track. This is important for the next stage in the circuitry: the analog to digital converter. This latter chip requires a stabile (constant level) input in order to successfully digitize it, which takes a finite time. Typically, 1 ms per bit of voltage resolution is required for accurate digitization. If for example the analog to digital converter is 16mms, then the track/hold chip most hold the signal at a constant level for at least 16 ms. Part description. Data Sheet.

ADC76

An analog to digital converter simply converts an analog signal to a digital one. It receives the output of the track/hold chip. This chip has several important specifications including the allowable input range and number of bits resolution, which were mentioned with respect to other components of the circuitry. The factors of: 1) allowable input voltage range and 2) the number of bits resolution go hand-in-hand in determining the voltage resolution. Typically, the allowable input voltage range is fixed at say, ± 10V. it means that the analog signal input to the chip must be within this range for accurate digitization. Any signal outside this range will not be properly digitized. It may be clipped (meaning that it will be set to +10V if the actually signal is greater than +10V, and set to -10V if the actual signal is less than -10V). Another possibility is that the signal is sometimes inverted (so instead of having a value of 11V, which is beyond the allowable range, the extra volt (10V + 1V) wraps around to 10V - 1V so that the digital output is 9V. Clearly, any form of distortion such as these is undesirable. So why amplify the original signal beyond the first stage gain which is necessary to keep the signal to noise ratio high? It is to maximize the voltage resolution, which requires adjusting the amplitude of the signal so that its maximum and minimum peaks approximately extend through the allowable input range of the chip. Let us take a simple two bit ADC as an example. Two bits represents four possible digital levels. If the analog input signal to the ADC is between -10V and -5V it will be represented by the lowest digital level when it is digitized (binary 00). If the analog input signal to the ADC is between -5V and 0V it will be represented by the next to lowest digital level when it is digitized (binary 01). If the analog input signal to the ADC is between 0V and +5V it will be represented by the next to highest digital level when it is digitized (binary 10). And If the analog input signal to the ADC is between +5V and +10V it will be represented by the highest digital level when it is digitized (binary 11). Say the first and second stage amplifiers only bring the amplitude of the signal to a level such that the absolute maximum peak is within the range of ± 5V. Then the highest and lowest digital levels would never be used! The 2 bit ADC would be effectively transformed into a 1 bit ADC, because there would be only a 1 bit voltage resolution. Hence, gaining to within the maximum allowable range (± 10V) is necessary to take maximum advantage of the number of bits digital resolution of the ADC, and therefore the voltage resolution of the chip. Data sheet for ADC76.

Once the sample point from one of the channels is digitized, the data can be sent to a storage device. To do this, it is placed on the data lines of a bus. A bus is a series of electrical connections imprinted on a circuit board, and a series of connectors. Each connector has a series of conductive tabs to which the wires are attached (one wire per tap). The tabs form a socket into which add-on (plug-in) boards can be placed. In this case, the add-on board is the data acquisition board containing the aforementioned components. He VME Bus was originally designed by Sun Computer and Motorola companies. However, it is an open standard, meaning anyone can use it. Being a "standard" means that there are official specifications for the types of materials and physical dimensions to be used for companies that want to construct VME busses and for companies that want to create plug-in boards that work with VME busses. There must be standards, or else the electronic products of different companies could never work with each other. Another standard is the "PC" standard. In research labs, one can choose to use a standard around which to develop biomedical circuitry, or not. In this case, we used the VME standard. Our acquisition board was designed to work with a VME bus. At its end is a VME connector, and it uses the data lines, power lines, and address lines (more about that later) that are as designated by the VME standard. Standards committees are set up by experts in industry, government, and academia. A large standards developing body is the IEEE (International Electrical and Electronics Engineers). Once a standard is developed through the IEEE, the IEEE publishes it in book form. Anyone can purchase standards by contacting the IEEE at their standards webpage or by telephone. It is also possible to serve on standards committees, depending on the engineer's expertise. Many times a company will like an employee to serve on a standards committee to help in its development. VME bus description and specs.

ALS573

The address decoder is an integrated circuit. The ALS573 accepts 8 inputs. It compares them to eight hard-wired values (i.e., it is an 8 bit comparator). This chip can be used to name each plug-in board. For example, board 3 will have the address 00000011. If the system is, say 320 channels, and each data acquisition board accepts 16 channels, then 20 data acquisition boards are needed. Twenty acquisition boards can be addressed with 5 bits (i.e., 2⁵ or 32_d (the subscript d stands for decimal). Therefore, there is no need to use all 8 bits of the address decoder. Only 5 will be used. The hard-wire pins for these 5 bits will be tied to either low or high voltage level (binary 0 or 1 respectively). For board 3, the lines would be tied as 00011: 1 for the least significant bit pin, 1 for the next least significant bit pin, and 0's for the other pins. These will be compared by using the compare pins on the decoder. The compare pins are connected to 5 address lines on the VME bus. When the address lines have the number 00011 on them, it signals board 3 to release its data to the VME bus data lines. The data (remember from the analog to digital converter we mentioned) is 16 bit; therefore it will require 16 data lines on the bus. By multiplexing on each board to produce one single channel whose sample point is digitized at any one time, and then by accessing a single data acquisition board at a time, only 16 data lines on the bus are needed to send the digital data to a digital storage device. If all channels data were accessed at once, it would require 16 x 320 = 5120 data lines. This is impractical - it would require a huge VME bus! In effect, accessing 1 of 20 data acquisition boards at a time is an additional multiplexing step. Data sheet for high speed CMOS (HCT), which has identical pinout to TTL chip.

WSB10

So, what drives the whole process? A signal generator board. One purpose for this type of board is to take a series of numbers from a data file and sends them sequentially to the appropriate lines on the bus. This is called broadcasting. So far we have learned that the numbers needed to be broadcast are the 5 address bits that access a particular board (1 of 20). But we spoke earlier of an 8:1 multiplex, a 2:1 multiple (combined 16:1 multiplex), a gain select, and an alias select. All of these digital commands can be done via the signal generator! For example let us say we would like to access signal 47. This would be channel 15 of board 3 (can you see why?). Let us suppose that the autogaining algorithm finds that the best second stage gain is 16. Let us say that the gate to select one of the 2 PGA100 outputs accepts a low signal for the first and a high signal for the second. Let us also suppose that we wish to use a low pass filter corner frequency of 500Hz and this requires a low command to the LTC1062. We could use the following binary number to command the system concerning this data:

alias/gain/channel/gate/board

0 100 1 110 00011

where 0 is the alias bit (low voltage), 100 is the gain (x16), 1 is the gate (second set of 8 channels on the board), 110 is the channel (7th) from the second set of 8 (i.e., channel 15), and 00011 is the board number (3).

Each time another sample point is to be digitized, a new binary word such as the one above is broadcast from the signal generation board. Typically during a given experiment, the autogaining procedure might be used several times to determine what is the best second stage gain to use to amplify each signal (it is used separately on each signal). After the autogain procedure, the gain determined for the particular channel, like channel 47 above, gain of 100, will remain constant until the next autogaining. Likewise for all other channels. Typically, the autogaining is done by a software program with a simple command typed onto the computer's command line such as "autogain". This procedure determines the best second stage gains for each channel at that particular moment in the experiment. During the course of the experiment, the preparation may change (or the transducer interface may change) resulting in the need for autogaining again. But in between autogaining procedures, the 2^nd, 3^rd, and 4^th bits of the command words like the one above will remain constant. Typically for the entire experiment, the alias word (which remember determines the LPF corner frequency) remains constant. So the first bit on the left will remain constant. Hence, the only bits that will change will be the right-hand 9 bits, which determine which channel is being accessed. If we go sequentially by channel number when digitizing the data, the command stream would then look like the following:

0 xxx 0 000 00001

0 xxx 0 001 00001

0 xxx 0 010 00001

0 xxx 0 011 00001

0 xxx 0 100 00001

0 xxx 0 101 00001

0 xxx 0 110 00001

0 xxx 0 111 00001

0 xxx 1 000 00001

0 xxx 1 001 00001

0 xxx 1 010 00001

But there is a problem with this if we want a fast digitization rate. Remember we mentioned that the ADC requires approximately 16m s to convert a single sample point. If we went in sequential order by channel number, it would mean that we would have to wait 16m s for channel 1 to be converted, 16m s for channel 2 to be converted, ... 16m s for channel 16 to be converted, which is a total of 256m s. That is a long time by computer standards! So, instead of doing it this way, we digitize in the following order:

0 xxx 0 000 00001

0 xxx 0 000 00010

0 xxx 0 000 00011

0 xxx 0 000 00100

0 xxx 0 000 00101

0 xxx 0 000 00110

0 xxx 0 000 00111

0 xxx 0 000 01000

0 xxx 0 000 01001

0 xxx 0 000 01010

0 xxx 0 000 01011

0 xxx 0 000 01100

0 xxx 0 000 01101

0 xxx 0 000 01110

0 xxx 0 000 01111

0 xxx 0 000 10000

0 xxx 0 000 10001

0 xxx 0 000 10010

0 xxx 0 000 10011

0 xxx 0 001 00000

0 xxx 0 001 00001

...

and so on. In other words, the first channel on each board is accessed starting with board 1, 2, 3, ... 20. Then the second channel from each board is accessed, starting with board 1, 2, 3, ... 3, and so on. When the access for the second channel from each board begins, it takes from each board the result of the analog to digital conversion of the first channel, which is stored in a buffer until it is needed. This buffer is called a "latch" meaning it latches onto the data when given the digital command to do so, and maintains the digital sample point in memory. Example of signal generator board.

ALS-573

This chip latches the digitized sample point as described above. It is a single memory buffer 8 bits wide. Therefore, two of these chips are needed to contain one 16-bit digital sample point. An input pin on this chip tells it when to latch the data. Where is the data coming from? From the output of the analog to digital converter chip. The lower 8 bits will go to one of the ALS-573’s and the upper 8 bits will go to the other ALS-573. There is another important input pin to command the ALS-573. This is to tell the chip whether its output pins should be in the high impedance state or not. If they are in the high impedance state, it is as though the output of the chip were disconnected to the next stage in the circuitry. In low impedance state, whatever digital data is stored in the memory of the chip will appear at the 8 output pins of each chip. It is important, because in fact the 8 output lines from each chip are connected to 16 data lines on the VME bus. Just as with address lines on the bus, the data lines are shared. It means that only one data acquisition board places data from its ADC onto the 16 VME bus data lines at any one time. All other data acquisition boards have their output pins from their ALS-573 chips in the high impedance state, while the one board that is being accessed places its data on the data lines of the VME bus.

121, 221 timers, and logic components.

This aspect of data acquisition is a little complicated. Suffice it to say that some of the commands to run the hardware components do not come directly from the signal generator board. Specifically, the command to track/hold SHC5320, convert the data using the ADC76, latch the data using the ALS-573, and command the ALS-573 output to be low or high impedance do not come directly from the signal generator board. Instead, these commands come from integrated circuits called timers. A timer is a chip that when commanded, will send out a digital pulse of varying length. The length of the pulse is controlled with a variable resistor (potentiometer) which is adjustable by hand. Upright and inverted pulses can be tapped from respective output pins of the timer. The idea is that several timers are used, and pulses with successively increasing pulse widths (delays) are sent to the SHC5320, ADC76, ALS-573 latch pin, and ALS-573 impedance out pin. Hence, in successive order, components on a particular data acquisition board are told to track/hold the data, digitize it, latch it, and broadcast it to the VME bus data lines. What starts the chain of events of timing pulses? It is the even of the particular number of the data acquisition board coming up on the VME bus address lines. It causes the address decoder to signal that the address of the board is being accessed, and the address decoder tells the timers to start their pulses to command the other chips.

Boolean logic is incorporated onto specialized IC's so that true/false questions having to do with data timing and validity can be tested. For example, the data might be allowed to proceed along the circuitry only if it has been received from the previous device AND the following device to which it is to be transmitted is ready to receive it. These kind of events require logic circuitry to implement. How it works.

This device usually consists of a plug-in board and software that reside in a dedicated computer. The board receives signals from the experiment in analog or digital form, and streams it in continuous mode to a digital storage device (usually a hard drive). Example: Data Translation DT3801 product description.

This device usually consists of a plug-in board and software that reside in a dedicated computer. The board receives signals from the experiment in analog or digital form, and displays them on the computer monitor in virtual oscilloscope mode (the computer screen is made to act like an oscilloscope). Example: Description of WinDaq virtual oscilloscope product from Dataq company.