The selected signal (1 of 16) proceeds to the sample and hold IC. The sample and hold tracks until commanded to hold (S/H pin). After the sample and hold chip maintains a stable output, the analog to digital converter (ADC) is commanded to convert the analog signal to digital (16 bits out). When the ADC has completed its task, it signifies this by driving the ready pin to the alternate logic level (hi or lo). At this point, the latch, or register, grabs the data at the command of the ready pulse from the ADC. Beyond the ADC, the data is digital, not analog, and consists of a 16 bit binary number. The two bytes of the binary number are signified by the green and blue leads. Once the digital sample point is latched, a command from the enable line tells the latch IC to send the 16-bit data onto the data lines of the VME bus (also shown as green and blue leads). When the board number that is being broadcast onto the VME Bus address lines, does not match that of a particular board, the output latch on this board is not enabled (it is instead set to high impedance) because the board decoder is not valid. Thus, the same 16 VME bus data lines can be used to transport data from each of many Data Acquisition Boards that we might have connected to the bus. Only that board whose board number is valid will enable the output latch to actually send data to the bus lines. Any other boards connected to the VME bus data lines will have high impedance outputs. If we forget and name two Data Acquisition Boards with the same number, there will be what is called "bus contention". It means that two or more devices will be fighting to drive the same bus lines, and the result will be spurious data further along in the system. Obviously, this problem must be remedied or the system will not work.

The command lines on the Data Acquisition Board (shown in red and orange) are very important because the signals which propagate along them are in fact commands which tell each IC when to operate and what to do. It all begins at the decoder IC at upper right. Suppose we dial in the binary number 00100 (decimal 4) to the decoder. The decoder also receives input from the address lines of the VME bus, shown in red into the decoder and also on the VME bus. When the 5 designated address lines that are connected to the decoder come up as 00100, the decoder signifies a match by changing the logic level (hi or lo) of its valid pin. This, in effect, is the signal which starts the chain of commands that get each chip working. First of all it enables the latch output, so that the 16-bit data word that was previously digitized and stored in the latch buffer is broadcast onto the data lines of the VME bus (for eventual storage into a mass storage device). The valid signal also goes to two Timer IC's. These chips put out a pulse of variable length. The length is varied by adjusting the resistance or capacitance (usually a potentiometer is used) that is an external part of the timer circuitry.

Why are timer pulses needed? Because a finite delay is needed to ensure that the signal has propagated to the next stage in the circuitry and stabilized. Certain of the VME address leads control the corner frequency of the LPF, the channel and gain select of the stage 2 amplifier / multiplexer, and the switch direction in the gate IC. The selected 1 or 16 input signals with the desired amplitude does not appear instantaneously at the S/H once the commands from the VME bus are received. It takes a finite time both for the propagation of the command signals, the data signal, and for the outputs of the IC's at each level to stabilize. Therefore, a delay is introduced before telling the S/H to hold the level of the output. This ensures that the input level that the S/H chip will be holding steady at its output is a stabile input with the correct gain and from the correct input channel. The S/H chip also needs time to stabilize its output to a constant level. Therefore, a longer pulse from a separate timer is used to tell the ADC when to convert the output signal from the S/H chip. The necessary delays we are talking about are on the order of microseconds. They are a very important concern particularly for those working on the cutting edge of microprocessor technology where devices are relaying data at gigahertz frequencies, rather than megahertz.

We have only shown one Data Acquisition Board. But if we would like to acquire more than 16 input channels of data, it is easily done by just adding more Data Acquisition Boards to the system. The VME bus can accept a maximum of 21 plug-in boards. Let us say that we use 20 of the slots for Data Acquisition Boards, then we would have a system capable of acquiring 16 x 20 = 320 channels of data. The only difference between these boards is that they would each be assigned a different board address number (at the switch that goes into the decoder at top right). These addresses would usually be designated by dip switches, would could be easily adjusted to each board to assign them numbers 1 to 20, for example. There are two components of the complete system that we will not go into detail about during this lecture. But we need to describe their basic function. One is the signal generator board. This board takes a list of numbers stored in a computer software file, and ports them out of the computer and onto the VME bus. If we use a commercially available PC compatible signal generator board, then we would control the signal generation from a PC, and it would be on the PC that the file containing addressing information would be stored. A cable is then used to end the addressing information from the output port of the signal generator board to the VME bus. Each addressing number that is broadcast onto the VME address lines (and correspondingly each number in the original software file) is 12 bits wide. Why? Count up the address and control lines in red on the Data Acquisition Schematic - you will find that there are 13 in total. Hence, each addressing word contains the board number (5 bits), channel number (3 bits plus 1 bit), gain to be used for second stage amplification (3 bits), and corner frequency for anti-aliasing (1 bit). Actually a 14^th command line is needed, from the signal generator, and that is the clock (shown in pink on the Data Acq board). Therefore, to acquire 1 digitized sample point from each of 320 analog channels, 320 addressing / control word must be clocked out from the signal generator board. The board is used in continuous mode, which simply means that once it has send out command information for each of the 320 data channels, it simply starts all over again, sending out the same information. To signify the start of a new set of 320 sample points, 1 from each of the 320 input channels, other circuitry (not shown) inserts a series of bytes called a "flag". Typically, a 3-byte flag is used, which only has 1 chance in 2²⁴ of appearing randomly in the data.

The other board that we would like to describe is the Display Board. A display board takes a part of the data and sends it to a display. There are at least two reasons for doing this. One is that by the use of appropriate electronic parts, one can include a switch by which any desired channel can be displayed. The second is that the displayed signal acts as a check that all of the circuitry is functioning properly. To display the data from a selected channel, we use the flag bytes described above so that the display circuitry can find the data from a particular channel. This is how it can be done. Firstly, the display board can acquire the 16-bit data that is broadcast onto the VME data lines. It does this transparently (it means it does not interfere with the normal course of data acquisition). The VME bus data lines on which the 16-bit digitized data from the Data Acq boards are broadcast are simply attached to a chip called a 2:1. This chip takes the 16 bit (two byte) wide word and halves it to 1 byte at the output. Whether the upper or lower bite (signified by green and blue) ends up at the output depends on the logic level of the clock select pin. If it is at logic lo, one byte will be selected to the output, and at logic hi the other byte is selected. The clock we use is a square wave, therefore alternately hi and lo byte of the 16 bit wide data words pass further along the board. These are sent down a series of buffers called a FIFO (first in first out). Three latch buffers are used, and at each, the 8-bit word is read by a corresponding decoder chip. Say our 3-byte flag word is A, B, C (in hexidecimal). If we dial in an A, a B, and a C on the three decoder chips, then when these particular bytes percolate through the FIFO, at the point that bytes A, B, and C arrive at their respective decoders, an 3-input "and" logic circuit will register that the byte on all three decoders is valid. The output from the "and" commands a chip called a binary counter to reset to all 0's at its 8 bit output. It then begins to count, one by one in binary, each time it receives a tick, or pulse, from the clock signal. Say we would like to view channel 20 on the display. If we dial in a 20 on the decoder chip associated with the binary counter, then when the counter has counted 20 clock pulses (i.e., when the digitized data word from the 20^th channel has arrived at the input to the Display Board (at the first latch), the decoder becomes valid. The valid command is sent to the digital to analog converter (DAC) to tell it to convert the digital data word, that it sees at the first latch, into an analog signal, to be send to an oscilloscope or other display system.